1. Field of the Invention
The present invention relates to a flash memory, and more particularly, to a flash memory with a protruded floating gate.
2. Description of the Prior Art
High-density nonvolatile memory devices have been receiving much attention for application in many fields. One of the most important factors is the low cost of the reduced size of each memory cell. However, it is very difficult to shrink the cell size in the fabrication of nonvolatile memory cells when the conventional local oxidation (LOCOS) isolation technique is used. The isolation structure formed by this technique has a very large dimension and thus limits the miniaturization of the memory cells.
Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the capacitive coupling ratio, which is a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.
The capacitive coupling ratio Cp is defined by:   Cp  =      Ccf          Ccf      +      Cfs                      where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.        
In order to improve programming and accessing speeds in nonvolatile memories, many attempts have been made to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp. For example, U.S. Pat. No. 6,171,909 discloses a method for forming a stacked gate of a flash memory cell. The coupling ratio of the stacked gate is increased by forming a conductive spacer. The conductive spacer, which is a portion of the floating gate, increases the capacitor area between the floating gate and control gate.
As shown in FIG. 1a, a conventional flash memory is comprised of a substrate 101, a gate oxide 104 forming on the substrate 101, a floating gate 105 forming on the gate oxide 104, a inter-gate oxide 106 forming on the floating gate 105, and a control gate 107 forming on the inter-gate oxide 106, wherein the substrate 101 has a source 102 and a drain 103. Traditionally, a high voltage is applied to the control gate 107 of the flash memory, and the electrons from the source 102 are injected into the floating gate 105 through the gate oxide 104. This programs the flash memory, e.g. writing information the flash memory, as shown in FIG. 1a. 
A erase is performed when a low voltage or no voltage is applied to the control gate 107 of the flash memory, and a high voltage is applied to the source 102, so that the electrons are injected into the source 102 through the gate oxide 104 thus erasing the flash memory.
When the flash memory is both programmed and erased, the electrons tunnel through the gate oxide 104. The gate oxide 104 is a thin layer, so that the gate oxide 104 is damaged after repeating several programming and erasing operations.